Design Verification Engineer - Redmond, WA & Menlo Park, CA

Company: Radiansys, Inc.
Location: Redmond
Posted on: September 14, 2020

Job Description:

Design Verification Engineer Menlo Park CA Full time role Experience Range 5 -7 Years Job Description Skill Requirement What are the top 3 "must have non-negotiable" skill sets that need to be present on a resume? System Verilog, UVM, Experience with writing testbench and testcases Preferable - DSPGPU blocktop level verification experience, OCPAMBA protocol experience Processor based blockSubsystem or SoC verification using CC++ Are there any specific certifications, educational background or portfolios that yoursquore looking for? No BE or ME EECECS would be ok. Are you open to candidates who can only work remote? Ok during COVID19 outbreak but prefer onsite working at FB office with us. RESPONSIBILITIES Write and augment existing testplans. Implement testbench and scoreboards checkers. Implement test sequences as per plan and debug failures Achieve 100 functional and code coverage Work closely with designers, micro architects fw to resolve issues Ability to communicate articulate clearly progress issues with project leads Skills MINIMUM QUALIFICATIONS 5 years of proven experience as a DV engineer Hands on experience with SV and UVM Hands on Experience with executable test plans and Coverage Driven verification Hands on Experience with Synopsys VCS Verdi or Cadence Incisive tools Familiarity with CC++ PREFFERED QUALIFICATIONS Python (or similar) scripting language ASIC design experience Experience in DSP based Audio or Computer Graphics or Compression' is desirable Education Bachelor's degree Required Skills ARTICULATE, ENGINEER, TEST PLANS, APPLICATION-SPECIFIC INTEGRATED CIRCUIT, ASIC Additional Skills ASIC DESIGN, C++, CADENCE, DEBUG, PYTHON, SCRIPTING, SYNOPSYS Thanks Krish Dagar RADIANSYS INC Contact (510) 213-7493 Email

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